By Charles E. Stroud
A contemporary technological develop is the artwork of designing circuits to check themselves, known as a integrated Self-Test. This e-book is written from a designer's point of view and describes the most important BIST methods which were proposed and carried out, in addition to their merits and boundaries.
Read or Download A Designer’s Guide to Built-In Self-Test (Frontiers in Electronic Testing) PDF
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Extra resources for A Designer’s Guide to Built-In Self-Test (Frontiers in Electronic Testing)
This algorithm provides the basic idea behind many ATPG programs . The algorithm can also be used to sensitize a path through combinational logic for delay fault testing. The basic algorithm is performed as follows: Step 1: At Step Step Step 34 the fault site, assign the logic value opposite to that of the stuck-at fault. This step is referred to as fault sensitization or fault activation. 2: From the fault site, choose a path to a primary output, assigning non-controlling logic values to all other inputs (referred to as off-path inputs) to gates in that path (1 = non-controlling logic value for AND/NAND gates and 0 = noncontrolling logic value for OR/NOR gates).
The transistor-level stuck fault model allows any transistor to be either stuckon (also referred to as stuck-short) or stuck-off (also referred to as stuck-open). 4 illustrates the emulation of the transistor-level stuck fault model in a 2input CMOS NOR gate. 4a gives the fault-free transistor-level diagram for the 2-input NOR gate. 4b). 4c (where the A-input N-channel MOSFET has been removed). Alternatively, stuck-on faults can be emulated by disconnecting the gate of the MOSFET from the signal net and connecting it to a logic 1 for N-channel transistors (NFETs) or to a logic 0 for Pchannel transistors (PFETs) such that the transistor is always conducting.
2 Fault Models and Detection To effectively evaluate the quality of a set of tests for a product, as well as to evaluate the effectiveness of a BIST approach in its application to that product, fault models are required for emulation of faults or defects in a simulation environment. The first requirement of a good fault model is that it accurately reflects the behavior of the actual defects that can occur during the fabrication and manufacturing processes as well as the behavior of faults that can occur during the operation of the system.